SAN FRANCISCO, Calif. - April 9, 2001 - CoWare™, Inc., the leading provider of system-level design tools, has enhanced the software flow and multi-processor design capabilities in its CoWare N2C™ design system, making this tool even better suited for platform-based design creation and usage. Enhancements to the software flow include flexibility to better integrate external software via the Build Manager, verification at different levels of software abstraction, enhanced debugging for software tasks, and easier integration via an RTOS Configurator capability. The multi-processor support now includes design support for multiple memory busses. These new capabilities will be demonstrated for the first time at the Embedded Systems Conference in San Francisco, April 9-12, 2001.

"Platform-based design is really catching on as the prevalent methodology for the creation and use of core-based architectures that can be rapidly extended and customized for a range of applications," stated CoWare Vice President Bob Moore. "Since software makes up a greater percentage of today's systems than hardware, these enhancements will help bridge the gap between the software and hardware teams."

Flexible Software Flow
CoWare improved the process of integrating software developed externally to the CoWare N2C environment with a new Build Manager. Externally developed software, including high-level drivers, custom RTOS, middleware and other embedded applications, can be delivered either in C source and header files, assembly files, object files, or as an achieve file. Software can be built for a specific processor (there may be more than one) and loaded at simulation time. CoWare N2C will re-generate the memory map header file, consisting of the addresses for all devices in the memory map as well as interrupt service routine entry point functions, whenever the system design changes. No manual updates are required. CoWare N2C now provides verification at various levels of abstraction for software development. Each level of software abstraction requires a different level of timing accuracy when verifying the complete system. As low-level drivers, middleware, operating systems and embedded appl! ications are developed, this software can be verified with the hardware model.

CoWare added several software-only views for debugging and optimizing embedded software tasks on the processor(s). Gantt charts help analyze how the task switching takes place. The CPU load view, useful for debugging and software optimization, shows the sharing of the processor power between different functions. The software task load view displays a graphical representation of the software task load spent on each task. The software function/thread call stack view shows the amount of time spent on the CPU by each function. The software task switching view helps analyze the timing between tasks. And the software task loading view helps analyze how processor power is shared between tasks, helping with optimization.

The new RTOS Configurator can be invoked during the software build whenever there are multiple threads or activities in the embedded software application. By specifying basic information such as the number of tasks, stack size of the task, entry point functions, priority, number of semaphores, number of FIFOs, and the size of the FIFOs, the user's preferred RTOS can be integrated to help in scheduling the software tasks.

Multi-Processor, Multi-Bus Support
Since more and more SoCs integrate multiple processors, CoWare extended its capabilities to manage single or multiple peripheral busses to single or multiple busmasters or CPUs. Multi-core Interface Synthesis support provides an easy method to partition software among the different processors. Along with partitioning and compilation capabilities, analysis views are provided so that the activity between the different processors may be captured. Each processor is configured separately to determine which software views are required.

Enhanced Platform-Based Design Capabilities
Platforms created in CoWare N2C give software designers an early, accurate model of the hardware to develop and test their software, so they don't have to wait for the hardware prototype to start software development. In addition, CoWare N2C includes powerful Interface Synthesis™ capabilities that automatically generate the software interfaces to the hardware using a clear, unambiguous Applications Programming Interface (API). This API consists of software files detailing the platform's memory map and software drivers, and automated assistance to build the software image and compile it onto the platform. This means that the software designer doesn't need to understand the details of the low-level driver routines and the design process is significantly faster.

Pricing and Availability
These new capabilities are currently available and are built into CoWare N2C at no extra charge.

About CoWare
CoWare, Inc., provides tools and methodologies that help engineering teams cut their system-on-a-chip design times in half. CoWare N2C( provides an efficient means to capture, analyze, and implement a system specification, with parallel development by hardware and software teams. In addition, CoWare N2C greatly enhances IP re-use and selection, further reducing design time. The CoWare N2C software is employed by major systems and semiconductor companies including Alcatel, Fujitsu, Matsushita, Mitsubishi, Motorola, Nokia, Sony and STMicroelectronics. CoWare is headquartered in Santa Clara, Calif. USA and employs over 130 people. For more information, visit www.CoWare.com.

Contact:
Jordi Ferrer
jordi@newiic.com
Newiic for Coware
www.coware.com
415-587-4464

CoWare, CoWare N2C, and Interface Synthesis are trademarks of CoWare, Inc.